Static random access memory (SRAM) cells or bitcells are commonly used in integrated circuits as a type of semiconductor memory that uses bistable latching circuitry to store each bit. SRAM can be fabricated on a silicon-on-insulator (SOI) substrate or a bulk silicon substrate with substantially the same operation principles. The term static differentiates it from dynamic RAM which must be periodically refreshed. SRAM bitcells have the advantageous feature of holding data without requiring a refresh. Some SRAM bitcells are single port, while some other SRAM bitcells are dual port. One typical SRAM bitcell is made up of six MOSFETs. Each bit in such a six transistor (6T) SRAM bitcell is stored on four transistors (two pull-up transistors and two pull-down transistors) that form two cross-coupled inverters. This storage cell has two stable states which are used to denote 0 and 1. Two additional access or pass-gate transistors serve to control the access to the 6T SRAM bitcell during read and write operations. The pass-gate transistors are thus utilized to read from or write into such a bitcell.
As lower power consumption is becoming a performance benchmark for microprocessors and system on chips (SoCs), 6T SRAM bitcells are designed to operate at a wide range of power supplies, including the minimum operating voltage (Vmin). Vmin generally refers to the lowest operating power supply level at which the bitcell can operate successfully for a given performance specification. The higher end of the wide range of power supplies allow the embedded memory arrays to operate faster at the cost of higher power dissipation, while the lower end of the wide range of power supplies allow the embedded memory arrays to operate at lower power dissipation, for example.
Yield is the fraction of working cells of all produced cells. The goal of every SRAM production is to reach a yield of close to 1. A bitcell will fail either due to read or write failure. If the SRAM bitcell it is not able to hold data, then the bitcell is considered a zero.
SRAM bitcells (or an array of SRAM bitcells), such as 6T SRAM bitcells, with improved Vmin and yield are therefore desirable.